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| HV2701 Initial Release Low Charge Injection 16-Channel High Voltage Analog Switch with Bleed Resistors Features HVCMOS technology for high performance Integrated bleed resistors on the outputs 16 Channels of high voltage analog switch 3.3V input logic level compatible 20MHz data shift clock frequency Very low quiescent power dissipation-10A Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches Flexible operating supply voltages General Description The Supertex HV2701 is a low charge injection 16-channel high voltage analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging and piezoelectric transducer drivers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data is shifted into a 16-bit shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed through noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Applications Medical ultrasound imaging NDT metal flaw detection Piezoelectric transducer drivers Optical MEMS modules HV2701 Block Diagram LATCHES D LE CL LEVEL SHIFTERS OUTPUT SWITCHES SW0 DIN CLK D LE CL SW1 16 BIT SHIFT REGISTER D LE CL SW2 DOUT D LE CL SW14 D LE CL SW15 VDD RGND GND LE CL VNN VPP NR102405 1 HV2701 Ordering Information Package Options DEVICE 48-Lead TQFP (1.4mm) HV2701 HV2701FG-G -G indicates package is RoHS compliant (`Green') Absolute Maximum Ratings VDD Logic supply VPP-VNN differential supply VPP Positive supply VNN Negative supply Logic input voltage Analog signal range Peak analog signal current/channel Storage temperature Power dissipation -0.5V to +7V 220V -0.5V to VNN+200V +0.5V to -200V -0.5V to VDD +0.3V VNN to VPP 3.0A -65C to 150C 1W *Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operation Conditions Symbol VDD VPP VNN VIH VIL VSIG TA Parameter Logic power supply voltage Positive high voltage supply Negative high voltage supply High level input voltage Low level input voltage Analog signal voltage peak-to-peak Operating free air temperature Value 3.0V to 5.5V 40V to VNN +200V -40V to -160V 0.9VDD to VDD 0V to 0.1VDD VNN+10V to VPP-10V 0C to 70C Notes: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2 VSIG must be within VNN and VPP or floating during power up/down transition. 3 Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. NR102405 2 DC Electrical Characteristics (over recommended operating conditions unless otherwise noted) 0C Sym Parameter Min Max 30 Small Signal Switch On-Resistance 25 25 18 23 22 RONS RONL RINT ISOL VOS IPPQ INNQ IPPQ INNQ ISW fSW Small Signal Switch On-Resistance Matching Large Signal Switch On-Resistance Value of output Bleed Resistor Switch Off Leakage per Switch* DC Offset Switch off* DC Offset Switch on* Quiescent VPP supply current Quiescent VNN supply current Quiescent VPP supply current Quiescent VNN supply current Switch output peak current Output switching frequency 6.5 IPP Average VPP supply current 4.0 4.0 6.5 INN Average VNN supply current 4.0 4.0 IDD IDDQ ISOR ISINK CIN Average VDD supply current Quiescent VDD supply current Data out source current Data out sink current Logic input capacitance 0.45 0.45 10 4.0 10 0.45 0.45 0.70 0.70 10 3.0 5.0 300 500 20 20 Min Typ 26 22 22 18 20 16 5.0 Max 38 27 27 24 25 25 20 Min Max 48 32 30 27 30 27 20 % ISIG = 5mA ISIG = 200mA ISIG = 5mA ISIG = 200mA ISIG = 5mA ISIG = 200mA +25C +70C Units HV2701 Conditions VPP = +40V VNN = -160V VPP = +100V VNN = -100V VPP = +160V VNN = -40V RONS ISIG = 5mA, VPP = +100V, VNN = -100V VSIG=VPP-10V, ISIG=1A Output Switch to RGND IRINT = 0.5mA VSIG = VPP-10V and VNN+10V No Load All switches off All switches off All switches on, ISW = 5mA All switches on, ISW = 5mA VSIG duty cycle < 0.1% Duty cycle = 50% VPP = +40V VNN = -160V 15 35 50 K 1.0 100 100 10 -10 10 -10 3.0 10 300 500 50 -50 50 -50 2.0 50 7.0 5.5 5.0 7.0 5.0 5.0 4.0 10 0.40 0.40 15 300 500 A mV mV A A A A 2.0 A kHz 8.0 5.5 5.5 8.0 5.5 5.5 4.0 10 mA A mA mA 10 pF mA mA VPP = +100V VNN = -100V VPP = +160V VNN = -40V VPP = +40V VNN = -160V VPP = +100V VNN = -100V VPP = +160V VNN=-40V fCLK = 5MHz, VDD = 5.0V All logic inputs are static VOUT = VDD-0.7V VOUT = 0.7V All output switches are turning On and Off at 50KHz with no load. * See Test Circuits on page 5 NR102405 3 AC Electrical Characteristics (over recommended operating conditions, VDD= 5.0V, tR= tF 5ns, 50% duty cycle, CLOAD= 20pF unless otherwise noted) Sym tSD tWLE Parameter Set Up Time Before LE Rises Time Width of LE 12 Clock Delay Time to Data Out Time Width of CL Set Up Time Data to Clock 7 Hold Time Data from Clock Clock Frequency Clock Rise and Fall Times Turn ON Time* Turn OFF Time* 2 8 20 50 5.0 5.0 20 dv/dt Maximum VSIG Slew Rate 20 20 -30 KO KCR IID CSG(OFF) CSG(ON) +VSPK -VSPK +VSPK -VSPK +VSPK -VSPK 820 QC Charge Injection* 600 350 * See Test Circuits on page 5 pC 150 Output Voltage Spike* 150 mV Off Isolation* -58 Switch Crosstalk* Output Switch Isolation Diode Current Off Capacitance SW to GND On Capacitance SW to GND 5.0 25 -60 300 17 50 5.0 25 12 38 -58 -60 -70 300 17 50 150 5.0 25 -58 -60 300 17 50 dB mA pF pF -30 -33 2 8 20 50 5.0 5.0 20 20 20 -30 dB 7 7 2 8 20 50 5.0 5.0 20 20 20 v/ns MHz ns s s ns 50 15 55 21 tSU tH fCLK tR,tF TON TOFF 100 40 50 15 55 21 12 78 30 100 40 12 50 15 55 21 ns 100 ns 40 ns VDD= 3.0V VDD= 5.0V VDD= 3.0 or 5.0V VDD= 3.0V VDD= 5.0V 0C Min 25 56 Max Min 25 56 +25C Typ Max +70C Min 25 56 ns Max Units ns VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD= 5.0V Conditions HV2701 tDO tWCL VSIG = VPP-10V, RLOAD = 10K VSIG = VPP-10V, RLOAD = 10K VPP = +40V, VNN = -160V VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V f = 5.0MHz, 1K//15pF load f = 5.0MHz, 50 load f = 5.0MHz, 50 load 300ns pulse width, 2.0% duty cycle 0V, f = 1.0MHz 0V, f = 1.0MHz VPP = +40V, VNN = -160V, RLOAD = 50ohm VPP = +100V, VNN = -100V, RLOAD = 50ohm VPP = +160V, VNN = -40V, RLOAD = 50ohm VPP= +40V, VNN= -160V, VSIG= 0V VPP= +100V, VNN= -100V, VSIG= 0V VPP= +160V, VNN= -40V, VSIG= 0V NR102405 4 HV2701 Test Circuits VPP-10V VPP-10V HV2701 Open RGND RGND RGND PP PP DD PP PP DD PP PP DD Switch Off Leakage per Switch DC Offset Switch ON/OFF TURN (TON/TOFF) ON/OFF TIME RGND RGND PP PP PP DD PP DD PP PP DD RGND OFF Isolation Output Switch Isolation Diode Current Switch Crosstalk RGND RGND PP PP PP DD PP DD Q = 1000pF x VOUT Charge Injection Output Voltage Spike NR102405 5 Logic Function Table INPUT DATA LATCH ENABLE CLOCK OUTPUT SWITCH HV2701 Notes: 1. 2. 3. 4. 5. 6. Th 16 switches operate independently. Serial data is clocked in on the L to H transition of the CLK. All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. DOUT is high when data in the register 15 is high. Shift registers clocking has no effect on the switch states if LE is high. The CL clear input overrides all other inputs. Logic Timing Waveforms DN-1 DATA IN 5 0% DN 50% DN+1 LE 50% 50% t WLE t SD 50% 50% th t DO CLOCK t SU DATA O UT 50% t OFF t ON V OUT (TYP ) OFF ON 90% 1 0% CLR 5 0% t WCL 5 0% NR102405 6 Pin Configuration and Package Outline - 48-Lead TQFP (1.4mm) (FG) Pin Name SW4B SW4A SW3B SW3A SW2B SW2A SW1B SW1A SW0B SW0A VNN VPP GND VDD DIN CLK LE CLR DOUT RGND SW15B SW15A SW14B SW14A SW13B SW13A SW12B SW12A SW11B SW11A SW10B SW10A SW9B SW9A SW8B SW8A SW7B SW7A SW6B SW6A SW5B SW5A NC HV2701 TQFP-48 3 4 5 6 7 8 9 10 11 12 13 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 38 39 40 41 42 43 44 45 46 47 48 1,2,14,16,35,36 0.055 0.004 (1.397 0.102) 0.354 0.01 (8.992 0.254) 0.275 0.004 (6.985 0.102) 0.354 0.01 (8.992 0.254) 0.008 0.003 (0.2032 0.0762) Pin 1 Pin 12 0.020 BSC (0.508) 0 - 7 0.275 0.004 (6.985 0.102) 0.059 0.004 (1.498 0.102) 0.039 (0.991) 0.024 0.008 (0.610 0.203) Measurement Legend = Dimensions in Inches Dimensions in Millimeters NC = No Internal Connection. Doc.# DSFP - HV2701 NR102405 7 |
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